Graduate Modelling Engineer (Graduate and Early Career)

United Kingdom
Today
Job Type
Permanent
Work Pattern
Full-time
Work Location
Hybrid
Seniority
Entry
Education
Degree
Visa Sponsorship
Available
Security Clearance
Required
Posted
30 Jun 2026 (Today)

Benefits

2–3 days in office (London or Bristol) Meaningful equity from day one Structured mentorship with experienced chip architects Modern, collaborative offices Rapid iteration with direct access to leadership

GRADUATE MODELLING ENGINEER

Graduate & Early Career · Pre-Silicon Engineering · London or Bristol · Hybrid

Most graduate roles in hardware put you in a queue. You inherit a task, run it through a flow someone else designed, and wait your turn to matter. This is not that.

At Fractile, the modelling team sits upstream of everything — the decisions made here shape the chip before RTL is written, before constraints are locked, before anyone else has a chance to course-correct. That means the work is high-stakes, intellectually demanding, and genuinely consequential from day one.

You will not be on a rotation programme. You will not be sitting in review meetings waiting for your turn to present. You will be contributing to architectural decisions that end up in silicon — working directly alongside engineers who have shipped chips at Arm, Intel, Apple, and Google, in a team small enough that your ideas get heard and your work has a name on it.

About Fractile

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world's most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

The frontier of AI is no longer a research problem. The tasks AI can complete are doubling in complexity every six to seven months, and the tokens required to complete them are scaling with it. Sequential reasoning — the kind that can't be parallelised away — means the internal clock speed of inference systems is the critical constraint. What stands between where we are today and the future potential of AI isn't smarter algorithms; it's the hardware to run them fast enough to matter.

Today's chips are hitting their wall. We're building the ones that don't.

Founded 2022 · 110+ people and growing · London & Bristol · Heart of the UK's frontier AI ecosystem

The Role

This is an early-career role for someone who wants to be at the point where hardware decisions get made — before RTL is written, before a floorplan exists, before the constraints are locked. Pre-silicon modelling is where architecture happens: where the questions are biggest, the trade-offs are hardest, and the answers have the most leverage.

Our ideal candidate has 0–3 years of experience, including recent graduates.

As a Graduate Modelling Engineer you will work within the modelling team, sitting at the intersection of hardware architecture, software systems, and ML inference. You will collaborate closely with colleagues across RTL design, verification, physical design, and system architecture — contributing to the decisions that shape the chip from the earliest stages of development through to tape-out.

We are not looking for someone from one specific background. Whether you come from a software and architecture route, a verification background, or have hands-on hardware design experience, what matters is that you are curious about how all the pieces fit together and motivated to work at the level where they connect.

At Fractile, we value ideas from everyone, regardless of title or tenure. You will be joining a culture where your curiosity is encouraged, your input matters, and there is real room to grow.

What You'll Do

  • Build and run functional and performance models of processor and accelerator microarchitecture, in C++ using SystemC.
  • Explore architectural trade-offs — cache sizing, memory bandwidth, datapath design, pipeline structure — and translate the results into clear guidance for the wider team.
  • Work with the verification team to develop functional models of hardware blocks that can be used both for simulation and as a reference for RTL checking.
  • Learn how ML inference workloads behave at the hardware level and what architectural choices serve them best.
  • Contribute to the simulation and tooling infrastructure that the architecture team depends on.
  • Engage in architecture discussions and bring the modelling perspective into decisions that span hardware and software.

The Mindset We Look For

  • A software mindset applied to hardware problems — or a hardware mindset with a desire to work upstream.
  • The desire to be in a high-impact role within a small, focused team.
  • Eagerness to improve working practices and build connections between hardware and software teams.
  • Detail-focused, with rigour as the baseline for all work.
  • Humility and a genuine desire to keep learning.
  • Comfortable in a fast-paced, open, and collaborative environment.

What We're Looking For

Background

  • A degree (BEng, MEng, MSc, or equivalent) in Computer Engineering, Electrical Engineering, Computer Science, Physics, or a related field — with a strong academic record and genuine interest in how hardware systems work.
  • Graduating in 2025 or 2026, or recently graduated — industry experience is not required.

Core Technical Skills

  • Strong software skills — C++ at a level where you have written something non-trivial. A simulator, a testbench framework, a data processing tool — something with real complexity.
  • Computer architecture fundamentals: cache hierarchies, pipeline stages, memory systems, instruction-level parallelism.
  • An ability to read, understand, and reason about digital hardware — whether that comes from RTL design, verification, or architectural coursework.

Desirable — Any Combination Is Welcome

  • Architecture simulation experience — gem5, custom cycle-accurate simulators, or equivalent, even from a university project.
  • Pre-silicon verification skills: testbench development, functional modelling of hardware blocks, stimulus creation, coverage closure.
  • Transaction-Level Modelling — in SystemC, UVM, or another methodology.
  • SystemVerilog — whether used for RTL design, verification, or both.
  • FPGA or ASIC implementation experience — at any level, including academic projects and tapeouts.
  • Familiarity with open-source silicon tools: Cocotb, Verilator, Icarus Verilog, gem5.
  • Exposure to ML accelerator architectures: systolic arrays, dataflow execution, custom ISA design.

Who Thrives Here

The candidates who stand out to us tend to have done more than their coursework required — a cache coherence simulator built from scratch to really understand MOESI, a testbench written because the existing one was not good enough, a RISC-V core implemented on FPGA for the satisfaction of seeing it run, or a decompiler for a game's custom bytecode because the problem was interesting. The project does not need to be large or polished. What it tells us is that you are genuinely engaged with this material.

We welcome applicants from across the hardware and software spectrum. If you have a verification background and want to move closer to architecture, this role gives you that path. If you have been working in physical design and want to understand the modelling decisions that drive the constraints you implement, this is where that knowledge becomes directly useful. If you are coming from a software and architecture route and want to see your simulations translate into real silicon, you will find that here too.

You do not need a prior industry role. Strong final-year or MSc project work, open-source contributions, or independent projects are equally compelling.

How We Work

  • Ownership and autonomy — you will have full agency to drive your work forward.
  • Rapid iteration — we work directly with leadership to move from idea to hardware on ambitious timelines.
  • Full-stack collaboration — hardware, software and modelling teams work closely together to create a product with generational impact.
  • A team-first mindset — the best idea gets shipped, regardless of where it comes from.

Why Fractile

  • Hybrid working — 2–3 days in our London (Farringdon) and Bristol offices.
  • Competitive graduate salary and meaningful equity from day one.
  • Structured mentorship within a small, high-calibre engineering team — you will work directly with experienced chip architects and modelling engineers, not sit in a graduate programme.
  • Modern, open offices with a collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative, and technical fluency.
  • We believe the hardest problems get solved by the broadest range of minds. We actively encourage applications from underrepresented groups in hardware and software engineering.

Export Control & Security Clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law. We will be transparent about this throughout the hiring process.

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